Silicides have been actively used in semiconductor device processes because of exhibiting low resistance, high thermal stability and easy adaptation to current silicon processes. Moreover, silicide layers formed on and/or over surfaces of a gate electrode and a source/drain junction may advantageously reduce a specific resistance of the gate electrode and a source/drain contact resistance respectively.
In particular, logic devices, which must realize a high speed operation, may have a serious problem in performance due to an increase in gate resistance and contact resistance. Although an attempt may be made to reduce a contact size from a structural viewpoint, this does not assure a desired contact resistance value and causes a delay at interconnections, thus making it impossible for the entire device to realize a high speed operation. Therefore, a silicide process to reduce a contact resistance is adopted. In a self-aligned silicide (salicide) process, silicide layers are formed simultaneously on and/or over surfaces of both a gate electrode and a source/drain junction due to a spacer present on and/or over a sidewall of the gate electrode.
As illustrated in FIG. 1A, a method for forming silicide in a semiconductor device can include forming gate dielectric layer 16 and gate electrode 18 on and/or over semiconductor substrate 10, such as a silicon substrate in which device isolation layer 12, well 14, etc. are formed. Lightly doped drain (LDD) region 20 is formed in substrate 10 between an edge of gate electrode 18 and device isolation layer 12. Spacer 22 is formed on and/or over a sidewall of gate electrode 18. Source/drain region 24 is formed in substrate 10 between an edge of spacer 22 and device isolation layer 12. Native oxide layer 26 may be formed on and/or over an upper surface of gate electrode 18. Similarly, a native oxide layer may be formed on and/or over an uppermost surface of source/drain region 24.
As illustrated in FIG. 1B, native oxide layer 26 and other impurities, which may be formed on and/or over the uppermost surfaces of gate electrode 18 and source/drain region 24, are removed via a pre-cleaning process. Thereafter, silicide metal layer 28 is formed on and/or over the entire surface of semiconductor substrate 10 by depositing a metal layer such as, e.g., a cobalt (Co) layer. Since cobalt (Co) used in the silicide metal layer 28 is easily oxidized upon exposure to air, capping layers 30, 32 may be formed on and/or over silicide metal layer 28 by sequentially depositing a metal layer such as, e.g., titanium (Ti) layer and/or titanium nitride (TiN) layer.
As illustrated in FIG. 1C, a primary annealing process is carried out to react silicon (Si) of semiconductor substrate 10 with cobalt (Co) of silicide metal layer 28, thus forming silicide layers 34 of cobalt monosilicide (CoSi) on and/or over the uppermost surfaces of both gate electrode 18 and source/drain region 24, respectively. Subsequently, semiconductor substrate 10, on and/or over which silicide layers 34 are formed, is subjected to a cleaning process using a cleaning solution such as, e.g., a sulfuric acid solution, to remove silicide metal layer 28 and capping layers 30, 32 which remain not having reacted during the primary annealing process, i.e., cobalt (Co)/titanium (Ti)/titanium nitride (TiN) residues on and/or over substrate 10. Thereafter, a secondary annealing process is carried out to convert cobalt monosilicide (CoSi) of silicide layers 34 into cobalt disilicide (CoSi2), which has a lower surface resistance.
With the above-described silicide forming method, it can be appreciated that capping layers 30, 32 are formed on and/or over silicide metal layer 28 in order to prevent silicide metal layer 28 from being exposed to air. However, if an excessive delay is encountered after forming silicide metal layer 28 and prior to carrying out the primary annealing process despite the above-described effort, an oxidation reaction may occur at an interface of semiconductor substrate 10 in contact with silicide metal layer 28. The growth of a native oxide layer due to the oxidation reaction causes liquid marks and deteriorates a reaction of silicon (Si) and cobalt (Co) during the following primary annealing process. This may result in silicide defects such as improper formation of silicide layers 34.